Minimization algorithms of number logic elements in implementation of linear mappings

Abstract: In the article, we propose an efficient algorithm to minimize the number of logic elements in the hardware implementation of large size linear mapping, presented by linear Boolean functions (LBF). The essence of the algorithm is to use the structural data on the description of the binary tree to determine the overall logic elements XOR. An algorithm based on obtained binary tree is constructed to synthesize logic schema.

Keywords: linear mapping, boolean function, minimization, implementation

For citation:
Borisenko N. P., Nguen V. L. Minimization algorithms of number logic elements in implementation of linear mappings. Doklady Tomskogo gosudarstvennogo universiteta sistem upravleniya i radioelektroniki, 2014, no. 3(33), pp. 118–128.