Abstract: The article describes a new algorithm for verification of residual errors in calibrated two-port vector network analyzers for wafer-level applications. Calibration residual errors are extracted from a distance-frequency system model with the Kotelnikov interpolation and special time-domain technique. Experimental studies were conducted at the wafer-level for the 110 GHz frequency band.
Keywords: vector network analyzer, s-parameters, calibration, probe station, on-wafer equipment, verification, systematic error
Authors and copyright holders:
—
For citation:
Savin A. A. Linear processing of verification data of vector network analyzer for wafer-level application. Doklady Tomskogo gosudarstvennogo universiteta sistem upravleniya i radioelektroniki, 2014, no. 3(33), pp. 53–57.
Last issue
-2025-1.jpg)
Editorial office address
Executive Secretary of the Editor’s Office
Editor’s Office: 40 Lenina Prospect, Tomsk, 634050, Russia
Phone / Fax: + 7 (3822) 701-582
Viktor N. Maslennikov
Executive Secretary of the Editor’s Office
Editor’s Office: 40 Lenina Prospect, Tomsk, 634050, Russia
Phone / Fax: + 7 (3822) 51-21-21 / 51-43-02
Subscription for updates
