Linear processing of verification data of vector network analyzer for wafer-level application

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Authors: Savin A. A.

Annotation: The article describes a new algorithm for verification of residual errors in calibrated two-port vector network analyzers for wafer-level applications. Calibration residual errors are extracted from a distance-frequency system model with the Kotelnikov interpolation and special time-domain technique. Experimental studies were conducted at the wafer-level for the 110 GHz frequency band.

Keywords: vector network analyzer, s-parameters, calibration, probe station, on-wafer equipment, verification, systematic error