Proceedings of TUSUR University / Archive / Issue of Journal № 1, t. 22, 2019 / Delay time of the signal in very-large integrated circuits

Delay time of the signal in very-large integrated circuits

DOI: 10.21293/1818-0442-2019-22-1-20-24

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Abstract
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Abstract: The method to calculate the delay time of a signal is proposed that allows to predict the magnitude of the signal delay taking into account parasitic components of inductance and capacitance of the metallization. The method is based on the results of modeling resistance, capacitance and inductance metallization in COMSOL Multiphysics. It is established that the contribution of the inductive component can be disregarded when the topological norm of ultra-large integrated circuits is reduced from 90 to 7 nm.

Keywords: vlsi metallization, submicron metallization, delay time, comsol

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For citation:
Danilina T. I., Chistoedova I. A., Zarechnev A. D. Delay time of the signal in very-large integrated circuits. Doklady Tomskogo gosudarstvennogo universiteta sistem upravleniya i radioelektroniki, 2019, vol. 22, no. 1, pp. 20–24. DOI: 10.21293/1818-0442-2019-22-1-20-24

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