Abstract: Fractional-N PLL synthesizer spur reduction technique is described. The block diagram of the synthesizer with the reduced level of spurs is given as a result and the algorithm of its operation is described.
Keywords: phase-locked loop, fractional-n pll synthesizer, the electronic two-position switch, phase detector, spurs
For citation:
Skotorenko I. V. Fractional-N PLL Synthesizer Spur Reduction Technique. Doklady Tomskogo gosudarstvennogo universiteta sistem upravleniya i radioelektroniki, 2011, no. 2(24), – p. 1. pp. 102–105.
Authors and copyright holders:
—
Last issue
-2026-1_%D0%BA%D0%BE%D0%BF%D0%B8%D1%8F.jpg)
Editorial office address
Executive Secretary of the Editor’s Office
Editor’s Office: 40 Lenina Prospect, Tomsk, 634050, Russia
Phone / Fax: + 7 (3822) 701-582
Viktor N. Maslennikov
Executive Secretary of the Editor’s Office
Editor’s Office: 40 Lenina Prospect, Tomsk, 634050, Russia
Phone / Fax: + 7 (3822) 51-21-21 / 51-43-02
Subscription for updates
